A prior art method of writing data to a flash memory is now described. A typical flash memory has a structure as shown in FIG. 1 and executes data writing (also called “programming”) and reading in a unit referred to as a page and erases data in a unit referred to as a block. In the example illustrated in FIG. 1, the NAND flash memory is composed of 8192 blocks (physical blocks), each having 64 pages. Furthermore, each page has four sectors in total; each of the four sectors consists of 512 bytes of user data and 16 bytes of ECC (Error Check Code) and management information, i.e., 528 bytes in total, as one ECC sector (an ECC sector is referred to as a “sector” in the present document).
A physical block address of the NAND flash memory is managed in correlation with a logical block address. When a host makes the NAND flash memory execute a data writing and/or reading operation, the host specifies its object address to the NAND flash memory (this address specified by the host is generally referred to as a “host LBA”). At this time, a controller of the NAND flash memory recognizes the host LBA as a logical block address of the NAND flash memory and finds a physical block address of the NAND flash memory corresponding to that logical block address by making reference to a table (referred to as a “logical block—physical block conversion table” in the present document) representing a correlation between the logical block address and the physical block address. Then, the controller confirms, on the basis of the physical block address, the page and sector of the physical block the host specifies as a beginning point for data writing and/or reading data (see FIG. 2). The host notifies the controller of the amount of data to be written (how many sectors) together with the host LBA.
When a data write command is derived by the host, it is necessary to rewrite data in a block by combining data that are not to be re-written and the data to be re-written and derived by the host; the combined data are written into an empty block in the NAND flash memory. The write process in response to the host issuing a command to write twelve (12) sectors of data (the number of sectors to be written from the host LBA as the head address) as described subsequently in connection with the description of the drawings.
Assume now that the host LBA finds that the sector from which the data rewriting is to be performed is the second sector (S1) of the fourth page (P3) of the physical block address 1 (PB1) as shown in FIG. 3. Then the controller initially searches an empty block not correlated with the logical block address (referred to herein as a “write block”). The empty block, i.e., block EB 8 (FIG. 2) copies to the write block the data of pages P0, P1 and P2 of physical block PB1 that are not to be rewritten (see FIG. 4). Because, in this example, the rewriting must be done from data of sector S1 of page P3 of physical block PB1, the controller reads data of sector S0 from page P3 in physical block PB1 to a buffer so sector S0 is transferred to the buffer (see FIG. 5). Next, the controller copies once to the buffer the transferred data of sector S0 of the fourth page (P3) of the write block (EB 8). This copying of sector S0 to page P3 of write block EB8 is in accordance with a NAND flash memory protocol and so eleven sectors of the write data sent from the host are written from the portion of sector S1 into page P3 of write block EB 8 (see FIG. 6). Because the final data of the twelfth sector are data that could not be written independently to a sector S0 of the seventh page (P6) of EB 8, sector data from sectors S1 to S3 of page P6 of physical block PB1 are transferred once to the buffer (see FIG. 7). Then, the controller writes the data of the twelfth sector sent from the host to sector S0 in page P6 of the write block EB 8 and then transfers the data that has been transferred to the buffer from PB1, to sectors S1, S2 and S3 of the write block (see FIG. 8).
Then, the controller copies the data from page P7 to the final page of physical block PB1 to write block EB 8 (see FIG. 9). Then, the controller erases all of the data written in physical block PB 1, updates the logical block—physical block conversion table and ends the process of one data write command from the host.
The NAND flash memory executes the write process described above every time the host issues a write command for the NAND flash memory. Therefore, the write process is relatively slow. In addition, because the life of the NAND flash memory depends on the number of data writing and erasing operations, the life of a NAND flash memory is relatively short when it is frequently operated by the previously described conventional method.